1. Field of the Invention:
This invention relates to a logic IC, and more particularly to an improvement of latch circuits provided to the logic IC for a scan-path testing.
2. Description of the Related Art:
In recent years, logic IC's have been developed to have a high integration density with an increase in number of logic circuits integrated in a single IC chip. One problem of such highly integrated logic IC is in testing of manufactured products If the test is carried out by applying all possible input signals to input terminals of the IC to be tested and detecting output signals to compare with expected logic values, an enormous period of time is required. This method is, in fact, ineffective for logic IC's of very large scale integration.
For time saving, a scan-path testing has been proposed. For the scan-path testing, the logic IC is provided with a plurality of flip-flops which are coupled with the combinational network in the logic IC to form a shift-register for inputting test signals and outputting internal signals. The test and internal signals are shifted through the shift-register in response to clock pulses. Although the same clock pulse is supplied to all the flip-flops, it is not identically applied due to differences between circuit paths from a clock terminal to respective flip-flops. If the application of the clock to one flip-flop becomes later than generation of an output from the preceding stage flip-flop, the output of the preceding stage flip-flop is errorneously set in the flip-flop to cause a shifting of signal through two or more stages in response to one clock pulse. Under such situation, a normal shift-register operation is no longer expected.
The errorneous shifting may be prevented by achieving the identical application of the clock signal to all the flip-flops. Therefore, the circuit for applying the clock signal to the flip-flops must be designed to have little stray capacitance. It is difficult to design such clock signal applying circuit having little stray capacitance.